1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device in which insertion loss is reduced.
2. Description of the Related Art
In mobile communication devices including mobile phones, microwaves in the GHz band are often used, and switch elements for switching high-frequency signals are often used for antenna switch circuits and transmitting/receiving switch circuits (e.g., Japanese Patent Application Publication No. Hei 9(1997)-181642). Since such elements deal with high frequencies, field effect transistors (hereinafter referred to as FETs) using gallium arsenide (GaAs) are often used as such elements. Along with this, monolithic microwave integrated circuits (MMICs) are being developed into which a switch circuit itself, such as described above, is integrated.
FIGS. 10A and 10B show circuit diagrams of compound semiconductor switch circuit devices using GaAs FETs and called a single-pole double-throw (SPDT) switch.
FIG. 10A is a fundamental circuit diagram. The sources (or drains) of first and second FETs FET1 and FET2 are connected to a common input terminal IN. The gates of the FET1 and FET2 are connected to first and second control terminals Ctl-1 and Ctl-2 through resistors R1 and R2, respectively. Further, the drains (or sources) of the FETs are connected to first and second output terminals OUT1 and OUT2, respectively. Signals which are applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals. Of the FETs, one to which an H-level signal is applied is turned on, whereby a high-frequency signal entering the input terminal IN is transmitted to either one of the output terminals. The resistors R1 and R2 are placed in order to prevent high-frequency signals from leaking through the gate electrodes to the DC potentials of the control terminals Ctl-1 and Ctl-2 which are AC grounded.
In the logic of the switch circuit shown in FIG. 10A, when a high-frequency signal is passed to the output terminal OUT1, a voltage of, for example, 3 V is applied to the control terminal Ctl-1 close to the output terminal OUT1, and a voltage of 0 V is applied to the control terminal Ctl-2. On the other hand, when a high-frequency signal is passed to the output terminal OUT2, a voltage of 3 V is applied to the control terminal Ctl-2 close to the output terminal OUT2, and a bias signal of 0 V is applied to the control terminal Ctl-1. However, depending on user demands, the inverse logic thereof needs to be constructed.
FIG. 10B shows the circuit configuration of the compound semiconductor switch circuit device where a logic pattern is reverse of one of FIG. 10A.
In this circuit, the gate of the FET1 is connected to the control terminal Ctl-1 located far from the FET1 through the resistor R1, and the gate of the FET2 is connected to the control terminal Ctl-2 located far from the FET2 through the resistor R2. In this configuration, when a signal is passed to the output terminal OUT1, a voltage of, for example, 3 V is applied to the control terminal Ctl-1 far from the output terminal OUT1, and a voltage of 0 V is applied to the control terminal Ctl-2. On the other hand, when a signal is passed to the output terminal OUT2, a voltage of 3 V is applied to the control terminal Ctl-2 far from the output terminal OUT2, and a bias signal of 0 V is applied to the control terminal Ctl-1.
FIGS. 11A and 11B show one example of a compound semiconductor chip into which a switch circuit of a reverse control type in the compound semiconductor switch circuit device shown in FIG. 10B is integrated. FIG. 11A is a plan view, and FIG. 11B is a cross-sectional view taken along the d—d line of FIG. 11A.
The FET1 and FET2 are placed in a central portion of a GaAs substrate. The resistors R1 and R2 are connected to gate electrodes 17 of the FETs. Further, pads I, O1, O2, C1, and C2, which respectively correspond to the common input terminal IN, the output terminals OUT1 and OUT2, and the control terminals Ctl-1 and Ctl-2, are provided around the FET1 and FET2 in the periphery of the substrate.
Incidentally, a Schottky metal layer indicated by dotted lines is a gate metal layer (Ti/Pt/Au) 20 which is formed simultaneously with the formation of the gate electrodes 17 of the FETs, and a wiring metal layer indicated by a solid line is a pad metal layer (Ti/Pt/Au) 30 which connects elements and which forms the pads. An ohmic metal layer (AuGe/Ni/Au) is ohmically connected to the substrate, and forms the source and drain electrodes of the FETs and extraction electrodes at both ends of the resistors. In FIG. 11A, the ohmic metal layer is not shown because it is overlapped by the pad metal layer.
Operating regions 12 are impurity regions indicated by dashed—dotted lines. In each of the operating region 12, source and drain regions are placed which are heavily-doped impurity regions. Source and drain electrodes 15 and 16 are connected to the source and drain regions. A gate electrode 17 forms a Schottky contact to the surface of the operating region 12. Further, comb-tooth shaped portions of the gate electrode 17 are bundled into a gate wiring 27 outside the operating region 12 and connected to a resistor.
In this case, the common input terminal pad I is a common pad of the two FETs FET1 and FET2, and each of the control terminal pads C1 and C2 is connected to the FET located far from itself. Further, the resistors R1 and R2, which are connections therebetween, are placed in parallel between the common input terminal pad I and the FETs. This technology is described for instance in Japanese Patent Application Publication No. 2002-368194.
As described above, in the switch circuit device of FIGS. 11A and 11B, in order to construct a switch circuit of a reverse control type, the resistors R1 and R2 are extended in the chip to be placed in parallel between the common input terminal pad I and the FETs.
Moreover, as show in FIG. 11B, in order to suppress the spread of depletion layers from the pads or the gate wirings 27, n+ type peripheral impurity regions 40 are provided in the peripheries of regions under the pads and the peripheries of regions under the gate wirings 27. Further, the resistors R1 and R2 are also made of n+ type impurity regions which are heavily-doped regions. Additionally, an opening is made in a nitride film 60, and the common input terminal pad I is provided. The distances between adjacent portions of the n+ type impurity region 40 under the common input terminal pad I and the resistors R1 and R2 are 4 μm each other.
This is because experimentally obtained data shows that when the distance between adjacent n+ type impurity regions is 4 μm or more in a compound semiconductor switch circuit device using GaAs FETs, isolation is 20 dB or more, that is, the isolation therebetween is ensured to be sufficient.
Thus, the resistors R1 and R2 can be placed in parallel between the common input terminal pad I and the FETs. Additionally, the resistors R1 and R2 and the common input terminal pad I can be closely placed at a distance of 4 μm from each other. Accordingly, an enlargement of the chip can be suppressed even if the chip has a reverse control pattern.
Here, the above-described switch circuit device has a pattern of FETs in which the operating regions 12 are formed by ion implantation of impurities into the GaAs substrate. This pattern can also be applied to the case of High Electron Mobility Transistors (HEMTs) in which the substrate structure is different.
However, when a switch circuit device was constructed in the same pattern as that of the above-described one using HEMTs instead of the GaAs FETs, it was revealed that insertion loss increased, which is loss in the transmission of a high-frequency signal from the common input terminal IN to the output terminal OUT1. This is because a pattern was adopted in which the distance between adjacent portions of the n+ type impurity region 40 under the common input terminal pad I and the resistor R1 is 4 μm.
The reason for this may be explained as follows: in the reverse control pattern, the resistor R1 extended from the control terminal pad C1 is located close to the common input terminal pad I; accordingly, part of an input high-frequency signal entering the common input terminal IN leaks through the n+ type impurity region 40 and the resistor R1 to the control terminal Ctl-1 which is at a GND potential at high frequencies.
That is, since the insertion loss of a HEMT is significantly small compared to that of a GaAs FET, an addition of insertion loss due to the aforementioned pattern shape, which addition was not observed in an MMIC using GaAs FETs, became apparent in an MMIC using HEMTs. The MMIC using GaAs FETs also potentially has an addition of insertion loss due to the aforementioned pattern shape by an amount similar to that in the MMIC using HEMTs. However, the addition of insertion loss was not observed, because the insertion loss of a GaAs FET itself is large and the proportion of the addition of insertion loss is negligible.